ATA ºê¸®Áö Çϵå¿þ¾î¸¦ ±¸ÇöÇÏÀÚ

 

ȸ·Îµµ 1

 

 

ȸ·Îµµ 2


 

Ç¥ 1 ºÎǰ ¸ñ·Ï


¢Â µé¾î°¡±â Àü¿¡

  Áö³­ È£¿¡¼­ ¿ì¸®´Â IEEE 1394¿Í ATA ºê¸®ÁöÀÇ °³³äÀ» »ìÆìº¸¾Ò´Ù. ÀÌÁ¦ º»°ÝÀûÀ¸·Î ºê¸®Áö º¸µå¸¦ Á¦ÀÛÇÒ °ÍÀε¥, Á¦ÀÛ¿¡ ¾Õ¼­ ÇÊ¿äÇÑ ºÎǰ°ú ±×°ÍµéÀÇ ±¸ÀÔ ¹æ¹ý µî¿¡ ´ëÇØ Àá±ñ ¾ð±ÞÇϰíÀÚ ÇÑ´Ù.

  ¿ì¼± °¡Àå ¸¹ÀÌ ¾²ÀÌ´Â ÀúÇ×°ú Ä¿ÆÐ½ÃÅ͸¦ Ĩ ŸÀÔÀ» »ç¿ëÇÏ¿´´Ù. º¸Åë ¸¸´É ±âÆÇ¿¡ ³³¶«À» ÇÒ ¶§¿¡´Â ´Ù¸®°¡ ÀÖ´Â ÀúÇ×°ú Ä¿ÆÐ½ÃÅ͸¦ »ç¿ëÇÑ´Ù. ÇÏÁö¸¸ ¸¹Àº ¼öÀÇ ºÎǰÀ» ³³¶«ÇÒ °æ¿ì¿¡´Â Ĩ ŸÀÔÀÌ ´õ È¿°úÀûÀÌ´Ù. Ĩ ÀúÇ×À̳ª Ä¿ÆÐ½ÃÅÍ Áß 2012 Å©±âÀÇ ºÎǰÀº ¸¸´É ±âÆÇÀÇ ±¸¸Û »çÀÌ¿¡ ³³¶«Çϱ⠾ȼº¸ÂÃãÀ̱⠶§¹®ÀÌ´Ù. Ĩ ŸÀÔÀº óÀ½¿¡ »ç¿ëÇϱⰡ ²¨·ÁÁöÁö¸¸ »ç¿ëÇϸé ÇÒ¼ö·Ï ½Ã°£°ú °ø°£À» Àý¾àÇÒ ¼ö ÀÖ´Ù. »ç½Ç ¿¹Àü¿¡´Â ³³¶«À» Çϰí ÀúÇ×À̳ª Ä¿ÆÐ½ÃÅÍÀÇ ´Ù¸®¸¦ Àß¶ó³»¾ß ÇÏ´Â ¹ø°Å·Î¿òÀÌ ÀÖ¾ú´Ù. ³³¶«À» ´Ù ³¡³»°í ¸¶Áö¸·¿¡ ´Ù¸®¸¦ Àß¶ó³»¸é µÈ´Ù°í ¸»ÇÏ´Â »ç¶÷µµ ÀÖÁö¸¸, ³³¶«À» ÇÏ´Â Áß°£Áß°£ ¸Å¿ì ºÒÆíÇÏ´Ù. ±×¸®°í ´ÙÇàÈ÷ ¿äÁòÀº Ĩ ŸÀÔÀÇ ÀúÇ×°ú Ä¿ÆÐ½ÃÅ͸¦ ¼Ò·®À¸·Î ½±°Ô ±¸ÇÒ ¼ö Àֱ⠶§¹®¿¡ ³³¶«¿¡ ÀÚ½ÅÀÌ ÀÖ´Â ºÐµéÀº ÀÌ ¹æ¹ýÀ» ±ÇÇÏ°í ½Í´Ù.

 

¢Â ºÎǰ ±¸¸Å °¡À̵å

 

  ÀúÇ×, Ä¿ÆÐ½ÃÅÍ, ´ÙÀÌ¿Àµå, ÀüÇØÄܵ§¼­, IDE 40ÇÉ ¼ÒÄÏ, 6ÇÉ 1394 ¼ÒÄÏ µî ºÎǰÀÇ ´ëºÎºÐÀº ¿ë»êÀ̳ª û°èõÀÇ ÀüÀÚºÎǰ »ó°¡¸¦ °¡¸é ½±°Ô ±¸ÇÒ ¼ö ÀÖ´Ù. ±×¸®°í µÎ °³ÀÇ ·¹±Ö·¹ÀÌÅÍ(U3, U4)µµ ½±°Ô ±¸ÇÒ ¼ö ÀÖ´Â °ÍÀ» ¼±ÅÃÇÏ¿´´Ù.

  ÇÏÁö¸¸ PHY(U2)¿Í OXFW911(U1)¸¦ ±¸Çϱâ À§Çؼ± ³ë·ÂÀÌ Á» ÇÊ¿äÇÒ °Í °°´Ù. ¿ì¼± PHY´Â ÅØ»ç½º ÀνºÆ®·ç¸ÕÆ®(TI, www.ti.com/sc/1394) ȨÆäÀÌÁö¿¡¼­ »ùÇà ½ÅûÀ» ÅëÇØ ±¸ÇÒ ¼ö ÀÖ´Ù. ÇÊÀÚ ¿ª½Ã »ùÇ÷Π¾òÀº ¿©¼¸ °³ÀÇ PHY¸¦ ÀÌ¿ëÇÏ¿© ºê¸®Áö¸¦ °³¹ßÇÏ¿´´Ù. µ¿ÀÏÇÑ Ä¨¿¡ ´ëÇØ ÃÖ´ë 3°³ÀÇ »ùÇÃÀ» ½ÅûÇÒ ¼ö Àִµ¥, °³¹ß ´ç½Ã(ÀÛ³â 9¿ù) º»ÀÎÀÌ ½ÅûÇÑ 3°³¸¦ ¸ðµÎ ½ÇÆÐÇØ µ¿·áÀÇ À̸§À¸·Î 3°³¸¦ ´õ ½ÅÃ»ÇØ¾ß¸¸ Çß´Ù.(¿©·¯ºÐÀº ÇÑ ¹ø¿¡ ¼º°øÇϱ⸦ Áø½ÉÀ¸·Î ±â¿øÇÑ´Ù) Ưº°ÇÑ ¹®Á¦°¡ ¾øÀ¸¸é 1ÁÖÀÏ ³»¿¡ UPS·Î »ùÇÃÀ» ¹Þ¾Æº¼ ¼ö ÀÖÀ» °ÍÀÌ´Ù. ¸¸¾à »ùÇà ½ÅûÀÌ °ÅÀý ´çÇÑ´Ù¸é, ´ëÁø¹ÝµµÃ¼¿Í °°Àº TIÀÇ ±¹³» µð½ºÆ®¸®ºäÅÍ¿¡ ¹®ÀÇÇϸé ĨÀ» ±¸ÇÒ ¼ö ÀÖÀ» °ÍÀÌ´Ù.

  OXFW911Àº Oxford SemiconductorÀÇ ±¹³» µð½ºÆ®¸®ºäÅÍÀÎ FM COM(www.fm.co.kr)À» ÅëÇØ ±¸ÇÒ ¼ö ÀÖ´Ù. °³¹ß ´ç½Ã 5°³¸¦ ÁÖ¹®ÇØ °¡½¿ Á¹À̸鼭 ³³¶«À» ÇÏ´ø ±â¾ïÀÌ ¾ÆÁ÷µµ »õ·Ï»õ·ÏÇÏ´Ù. ¿Ö³ÄÇϸé, Ĩ °ªÀÌ °³´ç 2¸¸¿øÀ¸·Î ²Ï ºñ½Õ°í ±×³ª¸¶µµ ±¸ÇϱⰡ ¾î·Á¿ü±â ¶§¹®ÀÌ´Ù. ´ç½Ã¿¡ ºñÇØ Áö±ÝÀº ±¹³»¿¡µµ 1394 ¿ÜÀåÇü HDD ÄÉÀ̽º¸¦ ÆÇ¸ÅÇϴ ȸ»ç°¡ ¸¹¾ÆÁ³À¸¹Ç·Î FM COM¿¡ Àç°í ¹°·®ÀÌ ¾î´À Á¤µµ ÀÖÀ» °ÍÀ̶ó »ý°¢µÈ´Ù. ¸¸¾à¿¡ FM COM¿¡ Àç°í ¹°·®ÀÌ ¾ø¾î¼­ ĨÀ» ±¸ÇÒ ¼ö ¾ø´Ù¸é ÇÊÀÚ°¡ ¸ö ´ã°í ÀÖ´Â ¸¼Àº±â¼ú(www.malgn.com)¿¡ ¹®ÀÇÇϱ⠹ٶõ´Ù. ¾Æ¸¶µµ ĨÀ» ±¸ÇÒ ¼ö ÀÖÀ» °ÍÀÌ´Ù. µ¶ÀÚ Á¦À§µéÀÇ °ÇÅõ¸¦ ºó´Ù. ^^

¢Â TSB41AB2 ? Physical Layer Controller (PHY)

 

 ±×¸² 1Àº TSB41AB2ÀÇ ÇÉ ¹èÄ¡µµÀÌ´Ù. 68ÇÉ PAP ÆÐŰÁöÀÌ´Ù.

 

±×¸² 1 Terminal Diagram of TSB41AB2


Ç¥ 2Àº TSB41AB2ÀÇ ±â´Éº° ÇÉ ºÐ·ùÇ¥ÀÌ´Ù.

 

Ç¥ 2 Terminal Functions of TSB41AB2

TERMINAL

DESCRIPTION

NAME

NO.

AGND

32,33,39,48,

49,50

Analog circuit ground

AVDD

30,31,42,51,

52

Analog circuit power. A combination of high-frequency decoupling capacitors near each terminal are suggested, such as paralleled 0.1 ¥ìF and 0.001 ¥ìF.

C/LKON

19

Bus manager contender programming input and link-on output

CNA

3

Cable-not-active output (leave unconnected)

CPS

24

Cable power status input. This terminal is normally connected to cable power through a 400k¥Ø resistor

CTL0

4

Control I/O. These bidirectional signals control communication between the TSB41AB2 and the LLC.

CTL1

5

D0

6

Data I/O. These are bidirectional data signals between the TSB41AB2 and the LLC.

D1

7

D2

8

D3

9

D4

10

D5

11

D6

12

D7

13

DGND

17,18,63,64

Digital circuit ground

DVDD

25,26,61,62

Digital circuit power. A combination of high-frequency decoupling capacitors near each terminal are suggested, such as paralleled 0.1 ¥ìF and 0.001 ¥ìF.

Filter0

54

PLL filter terminals

Filter1

55

 

nISO

23

Link interface isolation control input. If no isolation barrier is implemented (direct connection), the ISO terminal should be tied high

LPS

15

Link power status input

LREQ

1

LLC request input

PC0

20

Power class programming inputs. Programming is done by tying these terminals high or low. Refer to Table 3 for encoding.

PC1

21

PC2

22

PD

14

Power-down input. Leave unconnected

PLLGND

57,58

PLL circuit ground

PLLVDD

56

PLL circuit power. A combination of high-frequency decoupling capacitors near each terminal are suggested, such as paralleled 0.1 ¥ìF and 0.001 ¥ìF.

R0

40

Current setting resistor

R1

41

 

nRESET

53

Logic reset input. An internal pull-up resistor to VDD is provided so only an external delay capacitor is required

SE

28

Test control input. Tie to GND

SM

29

Test control input. Tie to GND

SYSCLK

2

System clock output. Provides a 49.152MHz clock signal, synchronized with data transfers, to the LLC.

TESTM

27

Test control input. Tie to DVDD

TPA0+

37

Twisted-pair cable A differential signal terminals. Board traces from each pair of positive and negative differential signal terminals should be kept matched and as short as possible to the external load resistors and to the cable connector.

TPA1+

46

TPA0-

36

TPA1-

45

TPB0+

35

Twisted-pair cable B differential signal terminals. Board traces from each pair of positive and negative differential signal terminals should be kept matched and as short as possible to the external load resistors and to the cable connector.

TPB1+

44

TPB0-

34

TPB1-

43

TPBIAS0

38

Twisted-pair bias output

TPBIAS1

47

XI

59

Crystal oscillator inputs. When an external clock source is used, XI should be the input and XO should be left open.

XO

60

 

  º¸´Ù ÀÚ¼¼ÇÑ ³»¿ëÀº TSB41AB2ÀÇ µ¥ÀÌÅÍ ½ÃÆ®¸¦ º¸¸é ¾Ë ¼ö ÀÖ´Ù. ÇÏÁö¸¸ µ¥ÀÌÅÍ ½ÃÆ®¸¦ ã¾Æ¼­ ÀÐ¾î º¸´Â °É ±ÍÂú¾Æ ÇÒ µ¶ÀÚµµ ÀÖÀ» °ÍÀ̱⿡ °£´ÜÈ÷ Á¤¸®ÇÑ °ÍÀÌ´Ù. À§ÀÇ ³»¿ëÀ» ¿ÏÀüÈ÷ ÀÌÇØÇÏÁö ¸øÇÑ´Ù°í ÇØµµ ºê¸®Áö¸¦ ¸¸µå´Â µ¥¿¡´Â Å« ¾î·Á¿òÀÌ ¾øÀ¸¸®¶ó »ý°¢ÇÑ´Ù. ¾Õ¿¡¼­ Á¦½ÃÇÑ È¸·Îµµ¸¦ À¯½ÉÈ÷ º¸¸é¼­ ³³¶«¸¸ Àß ÇÏ¸é µÇ´Â °ÍÀÌ´Ù.

´Ù¸¸ Áß¿äÇÑ(¶Ç´Â º»ÀÎÀÌ ¾î¶»°Ô ó¸®ÇØ¾ß ÇÒÁö ¸¹Àº °í¹ÎÀ» Çß´ø) ¸î °³ÀÇ Çɵ鿡 ´ëÇØ¼­´Â Ãß°¡ ¼³¸íÀ» Çϵµ·Ï ÇϰڴÙ. ±×¸®°í ȸ·Îµµ¿Í À§ Ç¥¸¦ ¹ø°¥¾Æ º¸¸é¼­ °¢ ÇÉÀÇ ¿¬°á »óŸ¦ È®ÀÎÇØ º¸±æ ±ÇÇÏ°í ½Í´Ù.(³ª¸§´ë·Î Àç¹ÌÀÖ°í »ÑµíÇÑ ÀÛ¾÷ÀÌ µÉÅ×´Ï¡¦)

  ¿ì¼± C/LKON(19) ÇÉÀ» »ìÆìº¸ÀÚ. ÀÌ ÇÉÀº Çϵå¿þ¾î ¸®¼Â(¿¹¸¦ µé¸é Àü¿ø ½ºÀ§Ä¡¸¦ Ä×À» ¶§)½Ã¿¡ ÄÁÅÙ´õ(contender) »óÅÂÀÇ ±âº»°ªÀ» ¼³Á¤Çϴµ¥ »ç¿ëµÈ´Ù. 10k¥Ø ÀúÇ×À» ÅëÇØ high(contender) ¶Ç´Â low(not contender)·Î ¼³Á¤ÇØ ÁÖ¸é µÇ´Âµ¥, µ¥ÀÌÅÍ ½ÃÆ®¿¡¼­´Â ÀÌ ÇÉÀ» low·Î ¼³Á¤Çϰí ÄÁÅÙ´õ »óÅ´ C ·¹Áö½ºÅÍ ºñÆ®¸¦ ÅëÇØ ¼³Á¤ÇØÁÖ´Â ¹æ¹ýÀ» ±ÇÇϰí ÀÖ´Ù.

  CPS(24) ÇÉ¿¡ »ç¿ëµÇ´Â 400k¥Ø ÀúÇ×Àº Ç¥ÁØ °ªÀÌ ¾Æ´Ï¶ó ½±°Ô ±¸ÇÒ ¼ö°¡ ¾ø´Âµ¥, ±Ù»ç°ªÀÎ 390k¥Ø ÀúÇ×À» »ç¿ëÇØµµ ¹«¹æÇÏ´Ù. ÀÏ¹Ý ÀúÇ×ÀÇ ¿ÀÂ÷ ¹üÀ§°¡ 5%À̹ǷΠ10k¥ØÀÇ Â÷ÀÌ´Â ¿ÀÂ÷ ¹üÀ§ ³»¿¡ µé¾î°¡±â ¶§¹®ÀÌ´Ù. Á¤»ó µ¿ÀÛ¿¡´Â ¾Æ¹«·± ¹®Á¦°¡ ¾ø´Ù.

  ´ÙÀ½À¸·Î power class¸¦ ¼³Á¤ÇÏ´Â PC0-PC2(20-22) ÇÉ¿¡ ´ëÇØ »ìÆìº¸ÀÚ. º» ÇÊÀÚ °³¹ßÃʱ⿡ ÀÌ ÇɵéÀ» ¾î¶»°Ô ó¸®ÇØ¾ß ÇÒ±î Á¤¸» ¸¹ÀÌ °í¹ÎÇß¾ú´Ù. ¾î¶»°Ô »ý°¢ÇØ º¸¸é ÀÌ°Ô ¸Â´Â °Í °°°í, ¶Ç ¾î¶»°Ô »ý°¢ÇØ º¸¸é Àú°Ô ¸Â´Â °Í °°°í¡¦ ³³¶«À» ´Ù ÇØ ³õ°í, ºÎǬ ¸¶À½¿¡ ÄÉÀ̺íÀ» ¿¬°áÇØ º¸¸é PC¿¡¼­ ¿ÜÀå Çϵå·Î ÀνÄÇÏÁö ¸øÇÏ´Â °æ¿ì°¡ Çã´ÙÇß´Ù. ±× ¶§¸¶´Ù power class ¼³Á¤¿¡ ¹®Á¦°¡ ÀÖ´Â °ÍÀΰ¡ °í¹ÎÇß¾ú´Ù. ÇÏÁö¸¸ ¾ÆÀÌ·¯´ÏÄÃÇϰԵµ ¿©·¯ ¹øÀÇ ½ÃÇà Âø¿À ³¡¿¡ ¾òÀº °á·ÐÀº power class ¼³Á¤ÀÌ Á¤»ó µ¿ÀÛ¿¡ Å« ¿µÇâÀ» ¹ÌÄ¡Áö ¾Ê´Â´Ù´Â °ÍÀ̾ú´Ù.

Ç¥ 3Àº 1394 Ç¥ÁØ¿¡¼­ Á¤ÀÇÇÑ power class °ü·Ã ³»¿ëÀÌ´Ù. ¿ì¸®°¡ ¸¸µé ºê¸®Áö´Â 1394 ÄÉÀ̺í·ÎºÎÅÍ °ø±ÞµÈ Àü¿ø(12V)À» ¿ì¼± 5V·Î ·¹±Ö·¹ÀÌÆÃÇϰí, À̰ÍÀ» ´Ù½Ã 3.3V·Î ·¹±Ö·¹ÀÌÆÃÇÏ¿© ·ÎÁ÷ Àü¿øÀ¸·Î »ç¿ëÇϹǷΠpower class¸¦ ¡®100¡¯À¸·Î ¼³Á¤ÇÏ¸é µÈ´Ù. ÇÏÁö¸¸ ÄÉÀ̺í·ÎºÎÅÍ Àü¿øÀ» °ø±Þ ¹Þ´Â °ÍÀÌ ¾Æ´Ï¶ó 5V¸¦ ¿ÜºÎ Àü¿ø¿¡¼­ º°µµ·Î °ø±ÞÇϰí À̰ÍÀ» 3.3V·Î ·¹±Ö·¹ÀÌÆÃÇÏ¿© »ç¿ëÇÒ ¶§¿¡µµ ¡®100¡¯ ¼³Á¤ÀÌ À¯È¿Çß´Ù. ÇÊÀÚÀÇ »ý°¢À¸·Ð °¡Àå ¹«³­ÇÑ ¼³Á¤ÀÌ ¾Æ´Ñ°¡ ½Í´Ù.(¡®may¡¯ÀÇ ÈûÀ̶ó°í³ª Çұ)

 

Ç¥ 3 Power Class Description

PC0-PC2

DESCRIPTION

000

Node does not need power and does not repeat power.

001

Node is self-powered and provides a minimum of 30 W to the bus.

011

Node may be powered from the bus for the PHY only using up to 3 W and may also provide power to the bus. The amount of bus power that it provides can be found in the configuration ROM.

101

Reserved

110

Node is powered from the bus and uses up to 3 W. An additional 3 W is needed to enable the link.

111

Node is powered from the bus and uses up to 3 W. An additional 7 W is needed to enable the link.

 

Áö³­ È£¿¡¼­µµ ¾ð±ÞÇßµíÀÌ, Á¦ÀÛÇÑ ºê¸®Áö¸¦ 2.5¡± HDD¿Í ÇÔ²² »ç¿ëÇÒ ¶§´Â ÃæºÐÇÑ Àü¿øÀ» HDD¿¡ °ø±ÞÇØ ÁÙ ¼ö ÀÖ´Ù(5V °ø±Þ). ÇÏÁö¸¸ 3.5¡± HDD¸¦ »ç¿ëÇÒ ¶§´Â º°µµÀÇ Àü¿ø °ø±Þ ÀåÄ¡°¡ ÇÊ¿äÇÏ´Ù. Å×½ºÆ®¸¦ ÇÒ ¶§¿¡´Â PC º»Ã¼ÀÇ ÆÄ¿ö ¼­ÇöóÀÌ¿¡¼­ ³²´Â Àü¿øÀ» ÀÌ¿ëÇØµµ µÇ°í, ½ÃÁß¿¡ ³ª¿Í ÀÖ´Â Àú·ÅÇÑ SCSI ¿ÜÀåÇü ÄÉÀ̽º¸¦ ¾à°£¸¸ º¯ÇüÇÏ¸é ½ÇÁ¦·Îµµ ÈǸ¢ÇÑ 1394 ¿ÜÀåÇü HDD·Î ¸¸µé¾î ¾µ ¼ö ÀÖ´Ù.

  ¸¶Áö¸·À¸·Î Àü¿øÇÉ(AVDD, DVDD, PLLVDD)µéÀ» ó¸®ÇÏ´Â ¹æ¹ýÀ» »ìÆìº¸ÀÚ. Ç¥¿¡µµ Á¤¸®ÇßµíÀÌ Àü¿øÇÉ °¡±îÀÌ¿¡ 0.1¥ìF°ú 0.001¥ìF Ä¿ÆÐ½ÃÅ͸¦ º´·Ä·Î Á¶ÇÕÇÑ °íÁÖÆÄ µðÄ¿Çøµ Ä¿ÆÐ½ÃÅ͸¦ ¹èÄ¡ÇÏ´Â °ÍÀÌ ÁÁ´Ù. ÀÌ´Â Àü¿øºÎÀÇ ³ëÀÌÁ Á¦°ÅÇϱâ À§ÇÑ °ÍÀÌ´Ù.


¢Â OXFW911 ? Link Layer Controller (LINK)

 

  OXFW911Àº IEEE 1394-1995, IEEE 1394a-2000 ±Ô¾àÀ» Áö¿øÇÏ´Â PHY¿Í ÇÔ²² »ç¿ëÇÏ¿© 1394 to ATA/ATAPI ºê¸®Áö¸¦ ±¸ÇöÇÒ ¼ö ÀÖµµ·Ï ÇØ Áִ ĨÀÌ´Ù. ÀÌ Ä¨ÀÇ ÄÚ¾î´Â ARM7TDMI(32bit RISC processor)À̸ç, 512kbÀÇ Ç÷¡½Ã ¸Þ¸ð¸®°¡ ³»ÀåµÇ¾î ÀÖ´Ù. Ĩ°ú ÇÔ²² Á¦°øµÇ´Â Æß¿þ¾î(firmware) ¾÷·Î´õ ÇÁ·Î±×·¥À» ÀÌ¿ë, 1394 ¹ö½º¸¦ ÅëÇØ ³»Àå Ç÷¡½Ã ¸Þ¸ð¸®¸¦ ÇÁ·Î±×·¡¹Ö ÇÑ´Ù. ´Ù½Ã ¸»Çϸé, ºê¸®Áö¸¦ Á¦ÀÛÇÑ ÈÄ 1394 ÄÉÀ̺í·Î ÄÄÇ»ÅÍ¿Í ºê¸®Áö¸¦ ¿¬°áÇÏ°í ³ª¼­ ¾÷·Î´õ ÇÁ·Î±×·¥À» ½ÇÇà½ÃŰ¸é µÈ´Ù(Æß¿þ¾î ¾÷·Îµå¿¡ ´ëÇØ¼­´Â ´ÙÀ½ È£¿¡¼­ ÀÚ¼¼ÇÏ°Ô ¼³¸íÇÒ °ÍÀÌ´Ù). PHY¿Í ¸¶Âù°¡Áö·Î 3.3V ´ÜÀÏ Àü¿øÀ¸·Î µ¿ÀÛÇÑ´Ù.

 ±×¸² 2´Â OXFW911ÀÇ ÇÉ ¹èÄ¡µµÀε¥ 128ÇÉ TQFP ÆÐŰÁöÀÌ´Ù.

 

±×¸² 2 Terminal Diagram of OXFW911

  Ç¥ 4´Â OXFW911ÀÇ ±â´Éº° ÇÉ ºÐ·ùÇ¥ÀÌ´Ù. ARM ¿ÜºÎ ÀÎÅÍÆäÀ̽º¿Í EEPROM ÀÎÅÍÆäÀ̽º´Â »ç¿ëÇÏÁö ¾ÊÀ» °ÍÀ̹ǷΠÀÌ ±â´É°ú °ü·ÃµÈ ÇɵéÀº Á¦¿ÜÇÏ¿´´Ù. ¿ª½Ã µ¥ÀÌÅÍ ½ÃÆ®¸¦ ÂüÁ¶ÇÏ¸é º¸´Ù ÀÚ¼¼ÇÑ ³»¿ëÀ» ¾Ë ¼ö ÀÖ´Ù.

 

Ç¥ 4 Terminal Functions of OXFW911

 

Name

Description

1394 PHY-LINK interface

104,105,108,109,110,

111,114,115

PD[7:0]

PHY-Link Data Bus

116,117

CTL[1:0]

PHY-Link Control Bus

119

PHYCLK

49.152 MHz clock sourced by PHY

121

LREQ

Link Request

102

LINKON

Requests link to power up when in a low power mode

103

LPS

Indicates to PHY that link is powered and ready

IDE interface

86,82,80,78,74,72,70,66,

65,69,71,73,77,79,81,85

ID[15:0]

IDE data bus

99,97,98

IA[2:0]

IDE address bus

101,100

ICS#[1:0]

IDE chip select. Used to select the Command Block or Control Block registers.

63

IDE_OE#

IDE output enable. Only used when external buffering is required to drive IDE data bus

64

IRESET

IDE interface reset

89

DMARQ

DMA request

90

DIOW#

IDE interface write strobe

91

DIOR#

IDE interface read strobe

92

IORDY

I/O ready

95

DMACK#

DMA acknowledge

62

INTRQ

Interrupt request

Miscellaneous Pins

56

RESET#

Global reset for the OXFW911. Active Low.

128

CKOUT

Clock output. 49.152 MHz clock output.

22,32,31

TEST_SEL,

TEST[1:0]

¡®100¡¯ = NORMAL OPERATION. Other settings are for foundry test purposes only.

57

UIF

Leave unconnected to use internal Flash, tie low to use only external device

Power and ground

15,8,40,48,59,76,94,107,

113

AC VDD

Supplies power to output buffers in switching (AC) state

30,21,23,68,84,88,120

DC VDD

Power supply. Supplies power to core logic, input buffers and output buffers in steady state

14,7,39,47,55,67,75,93,

96,106,112

AC GND

Supplies GND to output buffers in switching (AC) state

29,25,26,83,87,118

DC GND

Ground (0 volts). Supplies GND to core logic, input buffers and output buffers in steady state

Other

1,122

NC

Not Connect

 

  PHY¿¡ ºñÇØ LINK ĨÀº ÁÖÀÇ »çÇ×ÀÌ Àû´Ù°í ÇÒ ¼ö ÀÖ´Ù. ±×·¡µµ ¸î °¡Áö »ìÆìº¸µµ·Ï ÇÏÀÚ.

  IDE ÀÎÅÍÆäÀ̽º¿Í °ü·ÃµÈ ÇɵéÀº ¸ðµÎ 5V ÀÔÃâ·Â ½ÅÈ£¸¦ °ßµô ¼ö ÀÖµµ·Ï ¼³°è°¡ µÇ¾î ÀÖÁö¸¸, ÀϹÝÀûÀ¸·Î ȸ·Îµµ¿¡¼­¿Í °°ÀÌ 22 ¥Ø, 33 ¥Ø, 82¥Ø ÀúÇ×À» ÅëÇØ ¿¬°áÀ» ÇÑ´Ù.

  ±×¸®°í ¿ì¸®´Â ³»Àå Ç÷¡½Ã ¸Þ¸ð¸®¸¦ »ç¿ëÇÒ °ÍÀ̹ǷΠUIF(57) ÇÉÀ» not connect »óÅ·ΠµÎ¾î¾ß ÇÑ´Ù.

  ¸¶Áö¸·À¸·Î PHY¿¡¼­¿Í ¸¶Âù°¡Áö·Î power ÇÉ ÁÖº¯¿¡ ¾ÈÁ¤ÀûÀÎ µ¿ÀÛÀ» À§ÇØ Ä¿ÆÐ½ÃÅ͵éÀ» ¹èÄ¡Çϵµ·Ï ÇÑ´Ù.

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1. PHY - LINK

  PHY¿Í LINK´Â ÇÉ À̸§¿¡ ¸ÂÃç¼­ ±×´ë·Î ¿¬°áÀ» ÇÏ¸é µÈ´Ù. µÎ ĨÀÇ ÇÉ ¹èÄ¡°¡ ¼­·Î ¹Ì·¯(mirror) À̹ÌÁöÀ̱⠶§¹®¿¡ ²¿ÀÌ´Â ¼± ¾øÀÌ ¿¬°áÇÒ ¼ö ÀÖ´Ù. °³¹ß Ãʱ⿡ ´ë¸¸ÀÇ ºñ¾Æ(VIA)»ç¿¡¼­ ³ª¿Â PHY(VT6302)¸¦ »ç¿ëÇØ º¸±âµµ Çߴµ¥, ÀÌ Ä¨°ú OXFW911ÀÇ ÇÉ ¹èÄ¡ ¼ø¼­°¡ Á¤ ¹Ý´ë·Î µÇ¾î À־ ¼±ÀÌ ²¿ÀÌ´Â ¾ÆÇÄÀÌ ÀÖ¾ú´Ù.

  ÇÑ °¡Áö ÁÖÀÇÇÒ °ÍÀº 1394 ÀÎÅÍÆäÀ̽º°¡ ÃÖ´ë 400MbpsÀÇ °í¼ÓÀ¸·Î µ¥ÀÌÅ͸¦ Àü¼ÛÇÏ´Â °ÍÀ̹ǷΠ°¡´ÉÇÑ ÇÑ µÎ ĨÀÇ °Å¸®¸¦ ª°Ô ÇØ¾ß ÇÑ´Ù´Â °ÍÀε¥, ¾Æ·¡ÀÇ ±×¸²À» º¸¸é ±× ÀÌÀ¯¸¦ ½±°Ô ¾Ë ¼ö ÀÖ´Ù.

  ±×¸² 3Àº µÎ Ĩ »çÀÌÀÇ °Å¸®°¡ 20inch(1inch=2.54cm)·Î ¸Å¿ì ±æ ¶§ÀÇ »óȲÀ» ³ªÅ¸³½ °ÍÀÌ´Ù. 3ns(nano second, 1nano=10-9) ÀÌÈĸ¦ »ìÆìº¸ÀÚ. 3ns ÁîÀ½¿¡ ¿ÏÀüÇÑ ½ÅÈ£°¡ »ý¼ºµÇ¾ú´Âµ¥ ÇÑ ÂÊ ³¡(0inch)¿¡¼­´Â ¡®high¡¯ÀÌÁö¸¸ ´Ù¸¥ ÂÊ ³¡(20inch)¿¡¼­´Â ¿©ÀüÈ÷ ¡®low¡¯ÀÎ °ÍÀ» º¼ ¼ö ÀÖ´Ù. ÀÌ·¯ÇÑ Çö»óÀº 4ns ÀÌÈıîÁöµµ Áö¼ÓÀÌ µÇ°í ÀÖÀ¸¸ç, ½ÅÈ£ÀÇ integrity¸¦ ¶³¾î¶ß¸®´Â °á°ú¸¦ ÃÊ·¡ÇÑ´Ù.

±×¸² 3 Signal Traveling Over Long Wire

  ±×¸² 4´Â ¾Õ¿¡¼­¿Í °°Àº ½ÅÈ£¿¡ ´ëÇØ µÎ ĨÀÇ °Å¸®°¡ 1inch·Î ª¾ÆÁ³À» ¶§¸¦ ¹¦»çÇÑ °ÍÀÌ´Ù. ¸ðµç ½ÃÁ¡¿¡¼­ ¾ç´ÜÀÇ ½ÅÈ£°¡ Ç×»ó °ªÀ» °®°í ÀÖÀ½À» È®ÀÎÇÒ ¼ö ÀÖ´Ù. ½ÅÈ£ÀÇ ingrity°¡ À¯ÁöµÇ°í ÀÖ´Â °ÍÀÌ´Ù.

 

±×¸² 4 Signal Traveling Over Short Wire

 

2. PHY ? Cable connector (1394 connector)

  PHY¿Í 1394 Ä¿³ØÅÍÀÇ °Å¸® ¿ª½Ã ¸Å¿ì Áß¿äÇѵ¥, °á·ÐºÎÅÍ ¸»ÇÏÀÚ¸é ÀÌ °Å¸®µµ °¡´ÉÇÑ ÇÑ Âª°Ô ÇØ¾ß ÇÑ´Ù. Àü¼Û ¼Óµµ°¡ ¸Å¿ì ºü¸£±â ¶§¹®¿¡, °ü·Ã Çɰú Ä¿³ØÅ͸¦ ¿¬°áÇÏ´Â ¼±(³³¶«ÇÏ´Â ¼±)À» ÄÉÀ̺íÀÇ ¿¬ÀåÀ̶ó°í ºÁ¾ß ÇÑ´Ù. ÄÉÀ̺íÀº twisted pair(TP)·Î µÇ¾î Àִµ¥, TP ¶óÀο¡¼­ ½ÅÈ£ÀÇ Àü¾ÐÂ÷°¡ 110mV·Î ºñ±³Àû À۱⠶§¹®¿¡ ¾î¶°ÇÑ differential noise ¶óµµ Àü¼Û ½ÅÈ£¿¡ ¿µÇâÀ» ¹ÌÄ¥ ¼ö ÀÖ´Ù. ÀÌ·¯ÇÑ ÀÌÀ¯·Î ÀÎÇØ PHY¿Í Ä¿³ØÅÍÀÇ °Å¸®¸¦ °¡´ÉÇÑ ÇÑ Âª°Ô Çϰí, outer shied termination 󸮸¦ ÇØ ÁØ´Ù. ±×¸² 5, 6 ÂüÁ¶.

 

±×¸² 5 The PHY and Cable Connector

(±×¸² 5¿¡¼­ TSB41LV0x¸¦ TSB41AB2 ¼öÁ¤ÇØ ÁֽʽÿÀ)

 

±×¸² 6 Compliant DC Isolated Outer Shield Termination

 

 

¡®¹Ú½º±â»ç1_Å©¸®½ºÅ» ¹ßÁø ȸ·ÎÀÇ ±¸¼º¡¯À» ÀÌ ºÎºÐ¿¡ »ðÀÔÇØ ÁֽʽÿÀ.

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Áغñ¹°

ÀεÎ(SMD ³³¶«¿ë), ÀεΠ½ºÅĵå, ³³, Ç÷°½º, ·¡Çμ±, ´ÏÆÛ, ½ºÆ®¸®ÆÛ, ÇɼÂ

 

¡®¹Ú½º±â»ç2_³³¶« ¿ä·É ¹× ÁÖÀÇ »çÇס¯À» ÀÌ ºÎºÐ¿¡ »ðÀÔÇØ ÁֽʽÿÀ

 

  ÀÌÁ¦ ºÎǰµéÀ» ¾î¶»°Ô ¹èÄ¡ÇÒÁö °áÁ¤ÇßÀ¸¸®¶ó »ý°¢µÈ´Ù. µåµð¾î ³³¶«À» ÇÒ ½ÃÁ¡ÀÌ ¿Ô´Ù. Àγ»½ÉÀ» °®°í ³¡±îÁö ½Ç¼ö ¾øÀÌ ¸¶Ä¡±æ ±â¿øÇØ º»´Ù.

 

   ¾Æ·¡ÀÇ ±×¸²µéÀº ¸¸´É ±âÆÇ¿¡ Á¦ÀÛÇÑ ¿¹ÀÌ´Ù. Áö±ÝÀº ±ú²ýÇÏ°Ô Á¤¸®°¡ µÇ¾î ÀÖÁö¸¸ óÀ½ °³¹ßÇÒ ´ç½Ã¿¡´Â Á¤¸» º¹ÀâÇϱâ À̸¦ ¶§ ¾ø¾ú´Ù. ºÎǰ ¹èÄ¡ ¹× ³³¶«À» ÇÒ ¶§ ¸¹Àº µµ¿òÀÌ µÇ¸®¶ó »ý°¢ÇÑ´Ù.

 

±×¸² 7 ¾Õ¸é Àüü »çÁø

  SMD ŸÀÔÀÇ µÎ ĨÀ» ¸¸´É ±âÆÇ¿¡¼­ »ç¿ëÇϱâ À§ÇØ È®Àå º¸µå¸¦ »ç¿ëÇÒ ¼ö¹Û¿¡ ¾ø´Âµ¥ È®Àå º¸µåÀÇ Å©±â ¹®Á¦·Î ÀÎÇØ µÎ ĨÀ» ´õ ÀÌ»ó °¡±õ°Ô ÇÒ ¼ö ¾ø¾ú´Ù. À§ »çÁøÀ» ÂüÁ¶ÇÏ¿© 1394 Ä¿³ØÅÍ¿Í IDE Ä¿³ØÅÍ, ±×¸®°í Àü¿øºÎ¸¦ À§¿Í °°ÀÌ ¹èÄ¡ÇÏ¸é ºñ±³Àû ±ò²ûÇÏ°Ô ³³¶«À» ÇÒ ¼ö ÀÖÀ» °ÍÀÌ´Ù.

 

±×¸² 8 µÞ¸é Àüü »çÁø

 

±×¸² 9 PHY¿Í 1394 Ä¿³ØÅÍ ³³¶«

  PHYÀÇ power ÇÉµé °¡±îÀÌ¿¡ µðÄ¿Çøµ Ä¿ÆÐ½ÃÅ͵éÀÌ ¹èÄ¡µÇ¾î ÀÖÀ¸¸ç 1394 Ä¿³ØÅÍ¿Í PHY »çÀÌ¿¡ Á¸ÀçÇÏ´Â terminating ÀúÇ×µéÀÌ °¡±õ°Ô ¹èÄ¡µÈ °ÍÀ» È®ÀÎÇÒ ¼ö ÀÖ´Ù.

 

±×¸² 10 OXFW911 ³³¶«

  OXFW911ÀÇ power ÇÉµé °¡±îÀÌ¿¡ ¾ÈÁ¤ÀûÀÎ µ¿ÀÛÀ» À§Çؼ­ Ä¿ÆÐ½ÃÅ͵éÀ» ¹èÄ¡ÇÏ¿´´Ù.

±×¸² 11 40ÇÉ IDE Ä¿³ØÅÍ ³³¶«

  Ĩ ŸÀÔ ÀúÇ×À» »ç¿ëÇÏ´Â °ÍÀÌ ¾ó¸¶³ª ÆíÇÑÁö È®½ÇÇÏ°Ô ¾Ë ¼ö ÀÖÀ» °ÍÀÌ´Ù. ÀúÇ×ÀÇ ÇÑ ÂÊ ³¡À» Ä¿³ØÅÍ ÇÉ¿¡ Á÷Á¢ ºÙÀÌ¸é µÇ´Ï±î¡¦

±×¸² 12 Àü¿øºÎ ³³¶«

  Àü¿øºÎ´Â Ưº°ÇÑ ¾î·Á¿ò ¾øÀÌ ³³¶«ÇÒ ¼ö ÀÖÀ» °ÍÀÌ´Ù. ´Ù¸¥ ºÎºÐµé¿¡ ºñÇϸé ÀÌ°Ç Àϵµ ¾Æ´Ï¶ó°í ÇÒ ¼ö ÀÖÁö ¾ÊÀ»±î? ^^

¢Â Å×½ºÆ®¸¦ À§ÇÑ ½Ã½ºÅÛ ±¸¼º

 

  µåµð¾î ºê¸®Áö°¡ ¿Ï¼ºµÇ¾ú´Ù! (°¨µ¿ÀÇ ¹°°áÀÌ¡¦ ¿©±â±îÁö ¿À´À¶ó ¿©·¯ºÐµé Á¤¸» °í»ý ¸¹ÀÌ Çϼ̽À´Ï´Ù. ÀÌÁ¦ ¿Ï¼ºµÈ ºê¸®Áö°¡ Á¤»óÀûÀ¸·Î ÀÛµ¿ÇÏ´ÂÁö Å×½ºÆ® ÇÏ´Â Àϸ¸ ³²¾Ò±º¿ä.)

  Å×½ºÆ®¿¡ ¾Õ¼­ OXFW911¿¡ Æß¿þ¾î¸¦ ¾÷·Îµå ÇØ¾ß Çϴµ¥, ¾Õ¼­ ¸»ÇßµíÀÌ ÀÌ ºÎºÐÀº ´ÙÀ½ È£¿¡¼­ ¼³¸íÇÒ °ÍÀÌ´Ù. ´Ù½Ã ¸»Çϸé ÇöÀç·Î¼± Å×½ºÆ®¸¦ ÇÒ ¼ö ¾ø´Ù´Â °ÍÀÌ´Ù. ÇÏÁö¸¸ °í»ý°í»ý ³¡¿¡ Çϵå¿þ¾î Á¦ÀÛÀ» ¸ðµÎ ³¡¸¶Ãƴµ¥ ´ÙÀ½ ´Þ±îÁö Àý´ë·Î ±â´Ù¸®Áö ¸øÇϰڴٴ µ¶ÀÚ°¡ ÀÖ´Ù¸é ÇÊÀÚ¿¡°Ô °³ÀÎÀûÀ¸·Î ¸ÞÀÏÀ» º¸³»Áֱ⠹ٶõ´Ù.

  ´Ù¸¸ Å×½ºÆ®¸¦ À§ÇÑ ½Ã½ºÅÛ ±¸¼ºÀÇ ¿¹¸¦ º¸¿©ÁÖ´Â °ÍÀ¸·Î À̹ø ȸ¸¦ ¸¶Ä¡°íÀÚ ÇÑ´Ù. ¾Æ·¡ÀÇ ±×¸²À» º¸½Ã¶ó. ¿ì¼± PCÀÇ º»Ã¼¸¦ ¿­°í ³²´Â Àü¿ø ÄÉÀ̺íÀÌ ÀÖ´ÂÁö È®ÀÎÇØ º»´Ù. ´ÙÇàÈ÷ ³²´Â ÄÉÀ̺íÀÌ ÀÖ´Ù¸é ±×°É ÀÌ¿ëÇØ¼­ HDD¿¡ Àü¿øÀ» °ø±ÞÇØ ÁÖ¸é µÇ°í, Ȥ½Ã ³²´Â ÄÉÀ̺íÀÌ ¾ø´Ù¸é ½Ã½ºÅÛ HDD¸¦ Á¦¿ÜÇÑ ´Ù¸¥ ÀåÄ¡(¿¹¸¦ µé¸é CD-ROM)¿¡ ²ÈÇô ÀÖ´Â Àü¿ø ÄÉÀÌºí »Ì¾Æ¼­ ¾²¸é µÈ´Ù. ºê¸®Áö¿¡ ÇÊ¿äÇÑ Àü¿øÀº 1394 ÄÉÀ̺íÀ» ÅëÇØ °ø±ÞµÈ´Ù.

 

±×¸² 13 Å×½ºÆ®¸¦ ½Ã½ºÅÛ ±¸¼º ¿¹

 

¢Â ´ÙÀ½È£¿¡¼­´Â..

 

  ¿ì¼± ¿Ï¼ºµÈ ºê¸®Áö¿¡ Æß¿þ¾î¸¦ ¾÷·Îµå ÇÏ´Â ¹æ¹ýÀ» ÀÚ¼¼ÇÏ°Ô ¼³¸íÇÒ °ÍÀ̰í, ȯ°æ ¼³Á¤À» ¼öÁ¤ÇÏ´Â ¹æ¹ý±îÁö ¼³¸íÇϵµ·Ï ÇϰڴÙ. ±×¸®°í HDD, CD-R/RW, µÎ °³ÀÇ HDD, HDD & CD-R/RW µî ´Ù¾çÇÑ ¹æ¹ýÀ¸·Î PC¿¡ ¿¬°áÇÏ¿© »ç¿ëÇÏ´Â ¿¹¸¦ º¸¿©ÁÙ °ÍÀÌ´Ù. ¼Óµµ Å×½ºÆ® °á°úµµ ÇÔ²² Á¤¸®ÇÒ °ÍÀÌ´Ù.